High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops With Reset

The CD74HCT73 and CD74HCT73 utilize silicon Gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
These Flip-Flops have independent J, K, Reset and Clock inputs and Q and Q outputs. They change state on the negative-going transition of the Clock pulse. Reset is accomplished asynchronously by a low level input. This device is functionally identical to the HC/HCT107 but differs in terminal assignment and in some parametric limits.
The HCT Logic family is functionally as well as pin compatible with the standard LS Logic family.
By Texas Instruments
Part Manufacturer Description Datasheet Samples
CD74HCT73M Texas Instruments High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-SOIC -55 to 125
CD74HCT73ME4 Texas Instruments HCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, GREEN, PLASTIC, MS-012AB, SOIC-14
CD74HCT73EE4 Texas Instruments High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125
CD74HCT73MG4 Texas Instruments High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-SOIC -55 to 125
CD74HCT73M96 Texas Instruments HCT SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, PLASTIC, MS-012, SOIC-14
CD74HCT73E Texas Instruments High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset 14-PDIP -55 to 125
CD74HCT73 's PackagesCD74HCT73 's pdf datasheet
CD74HCT73E PDIP
CD74HCT73EE4 PDIP
CD74HCT73M SOIC
CD74HCT73ME4 SOIC
CD74HCT73MG4 SOIC




CD74HCT73 Pinout, Pinouts
CD74HCT73 pinout,Pin out
This is one package pinout of CD74HCT73,If you need more pinouts please download CD74HCT73's pdf datasheet.

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