3.3V PLL Clock Driver With 1/2x, 1x And 2x Frequency Options
The CDC2536 is a high-performance, low-skew, low-jitter Clock Driver It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the Clock output signals to the Clock input (CLKIN) signal. It is specifically designed for use with synchronous DRAMs and popular Microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC2536 operates at 3.3-V VCC and is designed to drive a 50-W transmission line. The CDC2536 also provides on-chip series-damping resistors, eliminating the need for external termination components. The feedback (FBIN) input is used to synchronize the output Clocks in frequency and phase to the input Clock (CLKIN). One of the six output Clocks must be fed back to FBIN for the PLL to maintain synchronization between CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN. The Y outputs CAN be configured to Switch in phase and at the same frequency as CLKIN. The select (SEL) input configures three Y outputs to operate at one-half or double the CLKIN frequency, depending on which pin is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the duty cycle at the input Clock Output-enable (OE) is provided for output control. When OE is high, the outputs are in the high-impedance state. When OE is low, the outputs are active. TEST is used for factory testing of the device and CAN be use to bypass the PLL TEST should be strapped to GND for normal operation. Unlike many products containing PLLs the CDC2536 does not require external RC networks. The loop Filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2536 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, as well as following any changes to the PLL reference or feedback signals. Such changes occur upon change of SEL, enabling the PLL via TEST, and upon enable of all outputs via OE.
The CDC2536 is characterized for operation from 0C to 70C.
By Texas Instruments
|CDC2536DBRG4||Texas Instruments||3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options 28-SSOP|
|CDC2536DL||Texas Instruments||3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options 28-SSOP|
|CDC2536DBR||Texas Instruments||3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options 28-SSOP|
|CDC2536DLR||Texas Instruments||3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options 28-SSOP|
|CDC2536DB||Texas Instruments||3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options 28-SSOP|
|CDC2536DBG4||Texas Instruments||3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options 28-SSOP|
|CDC2536 Pb-Free||CDC2536 Cross Reference||CDC2536 Schematic||CDC2536 Distributor|
|CDC2536 Application Notes||CDC2536 RoHS||CDC2536 Circuits||CDC2536 footprint|