3.3V PLL Clock Driver With 1/2x, 1x And 2x Frequency Options

The CDC536 is a high-performance, low-skew, low-jitter Clock Driver It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the Clock output signals to the Clock input (CLKIN) signal. It is specifically designed for use with synchronous DRAMs and popular Microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC536 operates at 3.3-V VCC and is designed to drive a 50-W transmission line.
The feedback input (FBIN) is used to synchronize the output Clocks in frequency and phase to the input Clock (CLKIN). One of the six output Clocks must be fed back to FBIN for the PLL to maintain synchronization between CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN.
The Y outputs CAN be configured to Switch in phase and at the same frequency as CLKIN. The select (SEL) input configures three Y outputs to operate at one-half or double the CLKIN frequency depending on which pin is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the duty cycle at the input Clock
Output-enable (OE) is provided for output control. When OE is high, the outputs are in the high-impedance state. When OE is low, the outputs are active. TEST is used for factory testing of the device and CAN be use to bypass the PLL TEST should be strapped to GND for normal operation.
Unlike many products containing PLLs the CDC536 does not require external RC networks. The loop Filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC536 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN as well as following any changes to the PLL reference or feedback signals. Such changes occur upon change of the select inputs, enabling the PLL via TEST, and upon enable of all outputs via OE.
The CDC536 is characterized for operation from 0C to 70C.
By Texas Instruments
Part Manufacturer Description Datasheet Samples
CDC536DB Texas Instruments 3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options 28-SSOP
CDC536DLR Texas Instruments 3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options 28-SSOP
CDC536DBR Texas Instruments 3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options 28-SSOP
CDC536DBRG4 Texas Instruments 3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options 28-SSOP
CDC536DL Texas Instruments 3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options 28-SSOP
CDC536DBG4 Texas Instruments 3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options 28-SSOP
CDC536DBLE Texas Instruments IC CDC SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28, PLASTIC, MO-150, SSOP-28, Clock Driver
CDC536 's PackagesCDC536 's pdf datasheet
CDC536DB SSOP
CDC536DBG4 SSOP
CDC536DBR SSOP
CDC536DBRG4 SSOP
CDC536DL SSOP
CDC536DLR SSOP

CDC536 pdf datasheet download


CDC536 Pinout, Pinouts
CDC536 pinout,Pin out
This is one package pinout of CDC536,If you need more pinouts please download CDC536's pdf datasheet.

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