3.3V PLL Clock Driver With 1/2x, 1x And 2x Frequency Options
The CDC586 is a high-performance, low-skew, low-jitter Clock Driver It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the Clock output signals to the Clock input (CLKIN) signal. It is specifically designed for use with popular Microprocessors operating at speeds from 50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC586 operates at 3.3-V VCC and is designed to drive a properly terminated 50- transmission line.
The feedback input (FBIN) is used to synchronize the output Clocks in frequency and phase to CLKIN. One of the twelve output Clocks must be fed back to FBIN for the PLL to maintain synchronization between the CLKIN input and the outputs. The output used as the feedback pin is synchronized to the same frequency as the CLKIN input.
The Y outputs CAN be configured to Switch in phase and at the same frequency as CLKIN. Select inputs (SEL1, SEL0) configure up to nine Y outputs, in banks of three, to operate at one-half or double the CLKIN frequency, depending on which pin is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLKIN.
Output-enable (OE) is provided for output control. When OE is high, the outputs are in the high-impedance state. When OE is low, the outputs are active. TEST is used for factory testing of the device and CAN be used to bypass the PLL TEST should be strapped to GND for normal operation.
Unlike many products containing PLLs the CDC586 does not require external RC networks. The loop Filter for the PLL is included on chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC586 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, as well as following any changes to the PLL reference or feedback signals. Such changes occur upon change of the select inputs, upon enabling of the PLL via TEST, and upon enable of all outputs via OE.
The CDC586 is characterized for operation from 0C to 70C.
By Texas Instruments
|CDC586PAHR||Texas Instruments||3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options 52-TQFP|
|CDC586PAHG4||Texas Instruments||3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options 52-TQFP|
|CDC586PAHRG4||Texas Instruments||3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options 52-TQFP|
|CDC586PAH||Texas Instruments||3.3V PLL Clock Driver with 1/2x, 1x and 2x Frequency Options 52-TQFP|
|SN54CDC586WD||Texas Instruments||3.3-V Phase-Lock-Loop Clock Driver With 3-State Outputs 56-CFP -55 to 125|
|SNJ54CDC586WD||Texas Instruments||3.3-V Phase-Lock-Loop Clock Driver With 3-State Outputs 56-CFP -55 to 125|
|CDC586 Pb-Free||CDC586 Cross Reference||CDC586 Schematic||CDC586 Distributor|
|CDC586 Application Notes||CDC586 RoHS||CDC586 Circuits||CDC586 footprint|