133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS

The CDC921 is a Clock Synthesizer driver that generates CPU, CPU_DIV2, 3V66, PCI APIC, 48MHz, and REF system Clock signals to support computer systems with a single Pentium III class Microprocessor All output frequencies are generated from a 14.318-MHz crystal input. Instead of a crystal, a reference Clock input CAN be provided at the XIN input. Two phase-locked loops (PLLs) are used to generate the host frequencies and the 48-MHz Clock frequency. On-chip loop Filters and internal feedback eliminate the need for external components. The host and PCI Clock outputs provide low-skew and low-jitter Clock signals for reliable Clock operation. All outputs have 3-state capability, which CAN be selected via control inputs SEL0, SEL1, and SEL133/100. The 48MHz Clock CAN be independently disabled via the control inputs SEL0, SEL1, and SEL133/100. In this state, the 48-MHz PLL is disabled and the 48MHz Clock is driven to high impedance to reduce component jitter. The outputs are either 3.3-V or 2.5-V single-ended CMOS Buffers With a Logic high-level on the PWR_DWN terminal, the device operates normally, but when a logical low-level input is applied, the device powers down completely with the outputs in a low-level output state. By Texas Instruments
CDC921 's PackagesCDC921 's pdf datasheet



CDC921 Pinout, Pinouts
CDC921 pinout,Pin out
This is one package pinout of CDC921,If you need more pinouts please download CDC921's pdf datasheet.

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