1.8V 1-to-10 High Performance Differential Clock Buffer

The CDCL1810 is a high-performance Clock distributor. The programmable dividers, P0 and P1, give a high flexibility to the ratio of the output frequency to the input frequency:
FOUT = FIN/P
Where:P (P0,P1) = 1, 2, 4, 5, 8, 10, 16, 20, 32, 40, 80
The CDCL1810 supports one differential LVDs Clock input and a total of 10 differential CML outputs. The CML outputs are compatible with LVDs receivers if they are ac-coupled.
With careful observation of the input voltage swing and common-mode voltage limits, the CDCL1810 CAN support a single-ended Clock input as outlined in the Pin Description Table.
All device settings are programmable through the SDA/SCL, serial two-wire Interface
The phase of one output group relative to the other CAN be adjusted through the SDA/SCL Interface For post-divide ratios (P0, P1) that are multiples of 5, the total number of phase adjustment steps (n) equals the divide-ratio divided by 5. For post-divide ratios (P0, P1) that are not multiples of 5, the total number of steps (n) is the same as the post-divide ratio. The phase adjustment step () in time units is given as:
= 1/(n FOUT)
where FOUT is the respective output frequency.
The device operates in a 1.8V supply environment and is characterized for operation from -40C to +85C. The CDCL1810 is available in a 48-pin QFN (RGZ) package.
By Texas Instruments