1:10 LVPECL/HSTL To LVPECL Clock DriverThe CDCLVP110 Clock Driver distributes one differential Clock pair of either LVPECL or HSTL (selectable) input, (CLK0, CLK1) to ten pairs of differential LVPECL Clock (Q0, Q9) outputs with minimum skew for Clock Distribution The CDCLVP110 CAN accept two Clock sources into an input multiplexer. The CLK0 input accepts either LVECL/LVPECL input signals, while CLK1 accepts an HSTL input signal when operated under LVPECL conditions. The CDCLVP110 is specifically designed for driving 50- transmission lines.
The VBB reference voltage output is used if single-ended input operation is required. In this case the VBB pin should be connected to CLK0 and bypassed to GND via a 10-nF capacitor. However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended. The CDCLVP110 is characterized for operation from ?40C to 85C. By Texas Instruments |
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| CDCLVP110 Pb-Free | CDCLVP110 Cross Reference | CDCLVP110 Schematic | CDCLVP110 Distributor |
| CDCLVP110 Application Notes | CDCLVP110 RoHS | CDCLVP110 Circuits | CDCLVP110 footprint |
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