1:10 LVPECL/HSTL To LVPECL Clock Driver

The CDCLVP110 Clock Driver distributes one differential Clock pair of either LVPECL or HSTL (selectable) input, (CLK0, CLK1) to ten pairs of differential LVPECL Clock (Q0, Q9) outputs with minimum skew for Clock Distribution The CDCLVP110 CAN accept two Clock sources into an input multiplexer. The CLK0 input accepts either LVECL/LVPECL input signals, while CLK1 accepts an HSTL input signal when operated under LVPECL conditions. The CDCLVP110 is specifically designed for driving 50- transmission lines.
The VBB reference voltage output is used if single-ended input operation is required. In this case the VBB pin should be connected to CLK0 and bypassed to GND via a 10-nF capacitor.
However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.
The CDCLVP110 is characterized for operation from ?40C to 85C.
By Texas Instruments
Part Manufacturer Description Datasheet Samples
CDCLVP110VFR Texas Instruments 1:10 LVPECL/HSTL to LVPECL Clock Driver 32-LQFP -40 to 85
CDCLVP110VFG4 Texas Instruments 1:10 LVPECL/HSTL to LVPECL Clock Driver 32-LQFP -40 to 85
CDCLVP110VF Texas Instruments 1:10 LVPECL/HSTL to LVPECL Clock Driver 32-LQFP -40 to 85
CDCLVP110VFRG4 Texas Instruments 1:10 LVPECL/HSTL to LVPECL Clock Driver 32-LQFP -40 to 85
CDCLVP110MVFRG4 Texas Instruments 1:10 LVPECL/HSTL to LVPECL Clock Driver 32-LQFP -40 to 85
CDCLVP110MVFR Texas Instruments 1:10 LVPECL/HSTL to LVPECL Clock Driver 32-LQFP -40 to 85
CDCLVP1102RGTT Texas Instruments Low Jitter 1:2 Universal-to-LVPECL Buffer 16-QFN -40 to 85
CDCLVP1102RGTR Texas Instruments Low Jitter 1:2 Universal-to-LVPECL Buffer 16-QFN -40 to 85
CDCLVP110 's PackagesCDCLVP110 's pdf datasheet
CDCLVP110MVFR LQFP
CDCLVP110MVFRG4 LQFP
CDCLVP110VF LQFP
CDCLVP110VFG4 LQFP
CDCLVP110VFR LQFP
CDCLVP110VFRG4 LQFP

CDCLVP110 pdf datasheet download


CDCLVP110 Pinout, Pinouts
CDCLVP110 pinout,Pin out
This is one package pinout of CDCLVP110,If you need more pinouts please download CDCLVP110's pdf datasheet.

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