Two LVPECL Output, High-Performance Clock Buffer

The CDCLVP1102 is a highly versatile, low additive jitter Buffer that CAN generate two copies of LVPECL Clock outputs from one LVPECL, LVDs or LVCMOS input for a variety of Communication applications. It has a maximum Clock frequency up to 2 GHz. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 10 ps, making the device a perfect choice for use in demanding applications. The CDCLVP1102 Clock Buffer distributes a single Clock input (IN) to two pairs of differential LVPECL Clock outputs (OUT0, OUT1) with minimum skew for Clock Distribution The inputs CAN be LVPECL, LVDs or LVCMOS/LVTTL. The CDCLVP1102 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended. The CDCLVP1102 is characterized for operation from –40°C to +85°C and is available in a QFN-16, 3-mm × 3-mm package. By Texas Instruments
Part Manufacturer Description Datasheet Samples
CDCLVP1102RGTR Texas Instruments Low Jitter 1:2 Universal-to-LVPECL Buffer 16-VQFN -40 to 85
CDCLVP1102RGTT Texas Instruments Low Jitter 1:2 Universal-to-LVPECL Buffer 16-VQFN -40 to 85
CDCLVP1102 's PackagesCDCLVP1102 's pdf datasheet

CDCLVP1102 Pinout, Pinouts
CDCLVP1102 pinout,Pin out
This is one package pinout of CDCLVP1102,If you need more pinouts please download CDCLVP1102's pdf datasheet.

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