Four LVPECL Output, High-Performance Clock Buffer

The CDCLVP1204 is a highly versatile, low additive jitter Buffer that CAN generate four copies of LVPECL Clock outputs from one of two selectable LVPECL, LVDs or LVCMOS inputs for a variety of Communication applications. It has a maximum Clock frequency up to 2 GHz. The CDCLVP1204 features an on-chip multiplexer (MUX) for selecting one of two inputs that CAN be easily configured solely through a control pin. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 15 ps, making the device a perfect choice for use in demanding applications. The CDCLVP1204 Clock Buffer distributes one of two selectable Clock inputs (IN0, IN1) to four pairs of differential LVPECL Clock outputs (OUT0, OUT3) with minimum skew for Clock Distribution The CDCLVP1204 CAN accept two Clock sources into an input multiplexer. The inputs CAN be LVPECL, LVDs or LVCMOS/LVTTL. The CDCLVP1204 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended. The CDCLVP1204 is packaged in a small 16-pin, 3-mm x 3-mm QFN package and is characterized for operation from –40°C to +85°C. By Texas Instruments
Part Manufacturer Description Datasheet Samples
CDCLVP1204RGTT Texas Instruments Low Jitter, 2-Input Selectable 1:4 Universal-to-LVPECL Buffer 16-VQFN -40 to 85
CDCLVP1204RGTR Texas Instruments Low Jitter, 2-Input Selectable 1:4 Universal-to-LVPECL Buffer 16-VQFN -40 to 85
CDCLVP1204 's PackagesCDCLVP1204 's pdf datasheet

CDCLVP1204 Pinout, Pinouts
CDCLVP1204 pinout,Pin out
This is one package pinout of CDCLVP1204,If you need more pinouts please download CDCLVP1204's pdf datasheet.

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