Four LVPECL Output, High-Performance Clock Buffer

The CDCLVP2102 is a highly versatile, low additive jitter Buffer that CAN generate four copies of LVPECL Clock outputs from two LVPECL, LVDs or LVCMOS inputs for a variety of Communication applications. It has a maximum Clock frequency up to 2 GHz. Each Buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 10 ps, making the device a perfect choice for use in demanding applications. The CDCLVP2102 Clock Buffer distributes two Clock inputs (IN0, IN1) to four pairs of differential LVPECL Clock outputs (OUT0, OUT3) with minimum skew for Clock Distribution Each Buffer block consists of one input that feeds two LVPECL Clock outputs. The inputs CAN be LVPECL, LVDs or LVCMOS/LVTTL. The CDCLVP2102 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended. The CDCLVP2102 is characterized for operation from –40°C to +85°C and is available in a QFN-16, 3-mm × 3-mm package. By Texas Instruments
Part Manufacturer Description Datasheet Samples
CDCLVP2102RGTR Texas Instruments Low Jitter, Dual 1:2 Universal-to-LVPECL Buffer 16-VQFN -40 to 85
CDCLVP2102RGTT Texas Instruments Low Jitter, Dual 1:2 Universal-to-LVPECL Buffer 16-VQFN -40 to 85
CDCLVP2102 's PackagesCDCLVP2102 's pdf datasheet
CDCLVP2102RGTR QFN
CDCLVP2102RGTT QFN




CDCLVP2102 Pinout, Pinouts
CDCLVP2102 pinout,Pin out
This is one package pinout of CDCLVP2102,If you need more pinouts please download CDCLVP2102's pdf datasheet.

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