12 LVPECL Output, High-Performance Clock Buffer

The CDCLVP2106 is a highly versatile, low additive jitter Buffer that CAN generate 12 copies of LVPECL Clock outputs from two LVPECL, LVDs or LVCMOS inputs for a variety of Communication applications. It has a maximum Clock frequency up to 2 GHz. Each Buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 20 ps, making the device a perfect choice for use in demanding applications. The CDCLVP2106 Clock Buffer distributes two Clock inputs (IN0, IN1) to 12 pairs of differential LVPECL Clock outputs (OUT0, OUT11) with minimum skew for Clock Distribution Each Buffer block consists of one input that feeds two LVPECL Clock outputs. The inputs CAN be LVPECL, LVDs or LVCMOS/LVTTL. The CDCLVP2106 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input pin. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended. The CDCLVP2106 is characterized for operation from –40°C to +85°C and is available in a QFN-40, 6-mm × 6-mm package. By Texas Instruments
Part Manufacturer Description Datasheet Samples
CDCLVP2106RHAR Texas Instruments Low Jitter, Dual 1:6 Universal-to-LVPECL Buffer 40-VQFN -40 to 85
CDCLVP2106RHAT Texas Instruments Low Jitter, Dual 1:6 Universal-to-LVPECL Buffer 40-VQFN -40 to 85
CDCLVP2106 's PackagesCDCLVP2106 's pdf datasheet
CDCLVP2106RHAR VQFN
CDCLVP2106RHAT VQFN




CDCLVP2106 Pinout, Pinouts
CDCLVP2106 pinout,Pin out
This is one package pinout of CDCLVP2106,If you need more pinouts please download CDCLVP2106's pdf datasheet.

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