Clock Buffer W/Programmable Divider, LVPECL I/O + Addl LVCMOS Output

The CDCM1802 Clock Driver distributes one pair of differential Clock input to one LVPECL differential Clock output pair Y0 and Y0 and one single-ended LVCMOS output Y1. It is specifically designed for driving 50- transmission lines. The LVCMOS output is delayed by 1.6 ns over the PECL output stage to minimize noise impact during signal transitions.
The CDCM1802 has two control pins, S0 and S1, to select different output mode settings. The S[1:0] pins are 3-level inputs. Additionally, an enable pin EN is provided to disable or enable all outputs simultaneously. The CDCM1802 is characterized for operation from ?40C to 85C.
For single-ended driver applications, the CDCM1802 provides a VBB output pin that CAN be directly connected to the unused input as a common-mode Voltage Reference
By Texas Instruments
CDCM1802 's PackagesCDCM1802 's pdf datasheet

CDCM1802 pdf datasheet download

CDCM1802 Pinout, Pinouts
CDCM1802 pinout,Pin out
This is one package pinout of CDCM1802,If you need more pinouts please download CDCM1802's pdf datasheet.

CDCM1802 Application circuits
CDCM1802 circuits
This is one application circuit of CDCM1802,If you need more circuits,please download CDCM1802's pdf datasheet.

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