1:3 LVPECL Clock Buffer With Programable Divider

The CDCP1803 Clock Driver distributes one pair of differential Clock inputs to three pairs of LVPECL differential Clock outputs Y[2:0] and Y[2:0] with minimum skew for Clock Distribution The CDCP1803 is specifically designed for driving 50- transmission lines. The CDCP1803 has three control terminals, S0, S1, and S2, to select different output mode settings. The CDCP1803 is characterized for operation from -40C to 85C. For use in single-ended driver applications, the CDCP1803 also provides a VBB output terminal that CAN be directly connected to the unused input as a common-mode Voltage Reference By Texas Instruments
CDCP1803 's PackagesCDCP1803 's pdf datasheet
CDCP1803RGER QFN
CDCP1803RGERG4 QFN
CDCP1803RGET QFN
CDCP1803RGETG4 QFN
CDCP1803RTHR QFN
CDCP1803RTHT QFN

CDCP1803 pdf datasheet download


CDCP1803 Pinout, Pinouts
CDCP1803 pinout,Pin out
This is one package pinout of CDCP1803,If you need more pinouts please download CDCP1803's pdf datasheet.

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