2.5V Phase Lock Loop Differential Clock Driver With 2-Line Serial Interface

The CDCV850 is a high-performance, low-skew, low-jitter zero delay Buffer that distributes a differential Clock input pair (CLK, CLK) to ten differential pairs of Clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback Clock outputs (FBOUT, FBOUT). The Clock outputs are controlled by the Clock inputs (CLK, CLK), the feedback Clocks (FBIN, FBIN), the 2-line serial Interface (SDATA, SCLK), and the Analog power input (AVDD). A two-line serial Interface CAN put the individual output Clock pairs in a high-impedance state. When the AVDD terminal is tied to GND, the PLL is turned off and bypassed for test purposes.
The device provides a standard mode (100 Kbits/s) 2-line serial Interface for device control. The implementation is as a slave/receiver. The device address is specified in the 2-line serial device address table. Both of the 2-line serial inputs (SDATA and SCLK) provide integrated pullup resistors (typically 100 k).
Two 8-bit, 2-line serial Registers provide individual enable control for each output pair. All outputs default to enabled at powerup. Each output pair CAN be placed in a high-impedance mode, when a low-level control bit is written to the control Register The Registers must be accessed in sequential order (i.e., random access of the Registers not supported). The serial Interface circuit CAN be supplied with either 2.5 V or 3.3 V (at VDDI) in applications where this programming option is not required (after power up, all output pairs will then be enabled).
When the input frequency falls below a suggested detection frequency that is below 20 MHz (typically 10 MHz), the output pairs are put into a high-impedance condition, the PLL is shut down, and the device will enter a low power mode. The CDCV850 is also able to track spread spectrum clocking for reduced EMI
Since the CDCV850 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL This stabilization time is required following power up, as well as changes to various 2-line serial Registers that affect the PLL The CDCV850 is characterized for both commercial and industrial temperature ranges.
By Texas Instruments
Part Manufacturer Description Datasheet Samples
CDCV850IDGGR Texas Instruments IC 850 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48, GREEN, PLASTIC, TSSOP-48, Clock Driver
CDCV850IDGGRG4 Texas Instruments IC 850 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48, GREEN, PLASTIC, TSSOP-48, Clock Driver
CDCV850IDGG Texas Instruments 2.5V Phase Lock Loop Differential Clock Driver with 2-Line Serial Interface 48-TSSOP -40 to 85
CDCV850DGG Texas Instruments 2.5V Phase Lock Loop Differential Clock Driver with 2-Line Serial Interface 48-TSSOP -40 to 85
CDCV850DGGG4 Texas Instruments 2.5V Phase Lock Loop Differential Clock Driver with 2-Line Serial Interface 48-TSSOP -40 to 85
CDCV850IDGGG4 Texas Instruments 2.5V Phase Lock Loop Differential Clock Driver with 2-Line Serial Interface 48-TSSOP -40 to 85
CDCV850DGGRG4 Texas Instruments 2.5V Phase Lock Loop Differential Clock Driver with 2-Line Serial Interface 48-TSSOP -40 to 85
CDCV850DGGR Texas Instruments 2.5V Phase Lock Loop Differential Clock Driver with 2-Line Serial Interface 48-TSSOP -40 to 85
CDCV850 's PackagesCDCV850 's pdf datasheet
CDCV850DGG TSSOP
CDCV850DGGG4 TSSOP
CDCV850DGGR TSSOP
CDCV850DGGRG4 TSSOP
CDCV850IDGG TSSOP
CDCV850IDGGG4 TSSOP
CDCV850IDGGR TSSOP
CDCV850IDGGRG4 TSSOP

CDCV850 pdf datasheet download


CDCV850 Pinout, Pinouts
CDCV850 pinout,Pin out
This is one package pinout of CDCV850,If you need more pinouts please download CDCV850's pdf datasheet.

CDCV850 Application circuits
CDCV850 circuits
This is one application circuit of CDCV850,If you need more circuits,please download CDCV850's pdf datasheet.


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