PLL Clock Driver For Synch. DRAM & Gen. Purp. Apps W/Spread Spectrum Compatibility, Power Down Mode
The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) Clock Driver It uses a PLL to precisely align, in both frequency and phase, the output Clocks (1Y[0?3] and CLKOUT) to the input Clock signal (CLKIN). The CDCVF2505 operates at 3.3 V. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50 percent, independent of duty cycle at CLKIN. The device automatically goes in power-down mode when no input signal is applied to CLKIN.
Unlike many products containing PLLs the CDCVF2505 does not require an external RC network. The loop Filter for the PLLs is included on-chip, minimizing component count, space, and cost.
Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference.
The CDCVF2505 is characterized for operation from ?40C to 85C.
By Texas Instruments
|CDCVF2505 Pb-Free||CDCVF2505 Cross Reference||CDCVF2505 Schematic||CDCVF2505 Distributor|
|CDCVF2505 Application Notes||CDCVF2505 RoHS||CDCVF2505 Circuits||CDCVF2505 footprint|