High Speec Super Low Power Sram

The CS18LV20483 is a high performance, high speed, and super low power CMOS Static Random Access Memory organized as 262,144 words by 8 bits and operates from a wide range of 2.7 to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.50uA and maximum access time of 55/70ns in 3.0V operation. Easy memory expansion is provided by an active LOW chip enable inputs (/CE1,CE2) and active LOW output enable (/OE) and three-state output drivers. The CS18LV20483 has an Automatic power down feature, reducing the power consumption significantly when chip is deselected. The CS18LV20483 is available in JEDEC standard 32-pin sTSOP (8x13.4 mm), TSOP (8x20mm), TSOP (II) (400mil) and SOP (450 mil) packages. By Unkown
CS18LV20483 's PackagesCS18LV20483 's pdf datasheet



CS18LV20483 Pinout, Pinouts
CS18LV20483 pinout,Pin out
This is one package pinout of CS18LV20483,If you need more pinouts please download CS18LV20483's pdf datasheet.

CS18LV20483 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

Related Electronics Part Number

Related Keywords:

CS18LV20483 Pb-Free CS18LV20483 Cross Reference CS18LV20483 Schematic CS18LV20483 Distributor
CS18LV20483 Application Notes CS18LV20483 RoHS CS18LV20483 Circuits CS18LV20483 footprint
Hot categories