18mb 1x1dp Lvcmos High Speed Synchronous Srams (256kb X 72 Or 512kb X 36) - Sony Corporation

The CXK79M72C165GB (organized as 262,144 words by 72 bits) and the CXK79M36C165GB (organized as 524,288 words by 36 bits) are high speed CMOS synchronous static RAMs with common I/O pins. They are manufactured in compliance with the JEDEC-standard 209 pin BGA package pinouts defined for SigmaRAM devices. They integrate input Registers high speed RAM, output Registers and a two-deep write Buffer onto a single monolithic IC. Single Data Rate (SDR) Pipelined (PL) read operations and Double Late Write (DLW) write operations are supported, providing a high-performance user Interface Positive and negative output Clocks are provided for applications requiring source-synchronous operation. All address and control input signals are registered on the rising edge of the CK input Clock During read operations, output data is driven valid once, from the rising edge of CK, one full cycle after the address and control signals are registered. During write operations, input data is registered once, on the rising edge of CK, two full cycles after the address and control signals are registered. Output drivers are series-terminated, and output impedance is selectable via the ZQ control pin. When ZQ is tied low, the impedance of the SRAMs output drivers is set to ~25. When ZQ is tied high or left unconnected, the impedance of the SRAMs output drivers is set to ~50. 333 MHz operation (333 Mbps) is obtained from a single 1.8V power supply. JTAG boundary scan Interface is provided using a subset of IEEE standard 1149.1 protocol. By Sony Electronics
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CXK79M36C165GB




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