Multi-Level Pipeline Register

The CY29FCT520T is a multilevel 8-bit-wide pipeline Register The device consists of four Registers A1, A2, B1, and B2, which are configured by the instruction inputs I0, I1 as a single four-level pipeline or as two two-level pipelines. The contents of any Register CAN be read at the multiplexed output at any time by using the multiplex-selection controls (S0 and S1). The pipeline Registers are positive-edge triggered, and data is shifted by the rising edge of the Clock input. Instruction I = 0 selects the four-level pipeline mode. Instruction I = 1 selects the two-level B pipeline, while I = 2 selects the two-level A pipeline. I = 3 is the hold instruction; no shifting is performed by the Clock in this mode. In the two-level operation mode, data is shifted from level 1 to level 2 and new data is loaded into level 1. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. By Texas Instruments
CY29FCT520T 's PackagesCY29FCT520T 's pdf datasheet
CY29FCT520ATPC PDIP
CY29FCT520ATPCE4 PDIP
CY29FCT520ATSOC SOIC
CY29FCT520ATSOCE4 SOIC
CY29FCT520ATSOCT SOIC
CY29FCT520ATSOCTE4 SOIC
CY29FCT520BTSOC SOIC
CY29FCT520BTSOCE4 SOIC
CY29FCT520BTSOCT SOIC
CY29FCT520BTSOCTE4 SOIC
CY29FCT520CTSOC SOIC
CY29FCT520CTSOCE4 SOIC
CY29FCT520CTSOCT SOIC
CY29FCT520CTSOCTE4 SOIC




CY29FCT520T Pinout, Pinouts
CY29FCT520T pinout,Pin out
This is one package pinout of CY29FCT520T,If you need more pinouts please download CY29FCT520T's pdf datasheet.

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