8-Bit Register

The FCT273T consists of eight edge-triggered D-type ip-ops with individual D inputs and Q outputs. The common buffered Clock (CP) and master reset (MR) load and reset all ip-ops simultaneously. The FCT273T is an edge-triggered Register The state of each D input (one set-up time before the LOW-to-HIGH Clock transition) is transferred to the corre- sponding ip-ops Q output. All outputs will be forced LOWby a low voltage level on the MR input. The outputs are designed with a power-off disable feature to allow for live insertion of boards. By Texas Instruments
CY54FCT273T 's PackagesCY54FCT273T 's pdf datasheet



CY54FCT273T Pinout, Pinouts
CY54FCT273T pinout,Pin out
This is one package pinout of CY54FCT273T,If you need more pinouts please download CY54FCT273T's pdf datasheet.

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