8-Bit Register

The FCT377T has eight triggered D-type ip-ops with individual D inputs. The common buffered Clock inputs (CP) loads all ip-ops simultaneously when the Clock Enable (CE) is LOW. The Register is fully edge-triggered. The state of each D input, one set-up time before the LOW-to-HIGH Clock transition, is transferred to the corresponding ip-ops O out- put. The CE input must be stable only one set-up time prior to the LOW-to-HIGH Clock transition for predictable operation. The outputs are designed with a power-off disable feature to allow for live insertion of boards. By Texas Instruments
CY54FCT377T 's PackagesCY54FCT377T 's pdf datasheet



CY54FCT377T Pinout, Pinouts
CY54FCT377T pinout,Pin out
This is one package pinout of CY54FCT377T,If you need more pinouts please download CY54FCT377T's pdf datasheet.

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