32K/64K X16/18 Synchronous Dual Port Static RAM

The CY7C09289 CY7C09279 and CY7C09389 CY7C09379 are high-speed syn- chronous CMOS 32K, and 64K x 16/18 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous [5] access for reads and writes to any location in memory. Reg- isters on control, address, and data lines allow for minimal set- up and hold times. In pipelined output mode, data is registered [1] for decreased cycle time. Clock to data valid t = 6.5 ns CD2 (pipelined). Flow-through mode CAN also be used to bypass the pipelined output Register to eliminate access latency. In flow-through mode data will be available t = 15 ns after the CD1 address is clocked into the device. Pipelined output or flow- through mode is selected via the FT/PIPE pin. By Cypress Semiconductor Corp.
CY7C09289 's PackagesCY7C09289 's pdf datasheet
CY7C09279-6AC TQFP
CY7C09279-7AC TQFP
CY7C09279-9AC TQFP
CY7C09279-12AC TQFP
CY7C09289-6AC TQFP
CY7C09289-7AC TQFP
CY7C09289-9AC TQFP
CY7C09289-9AI TQFP
CY7C09289-12AC TQFP
CY7C09379-6AC TQFP
CY7C09379-7AC TQFP
CY7C09379-9AC TQFP
CY7C09379-12AC TQFP
CY7C09389-6AC
CY7C09389-7AC
CY7C09389-9AC
CY7C09389-9AI
CY7C09389-12AC
CY7C09279




CY7C09289 Pinout, Pinouts
CY7C09289 pinout,Pin out
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