3.3V 16K/32K X 36 FLEx36? Synchronous Dual-Port Static RAM

The CY7C09569V and CY7C09579V are high-speed 3.3V synchronous CMOS 16K and 32K x 36 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is regis- tered for decreased cycle time. Clock to data valid t = 5 ns CD2 (pipelined). Flow-through mode CAN also be used to bypass the pipelined output Register to eliminate access latency. In flow-through mode data will be available t = 12.5 ns after CD1 the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/Pipe pin. By Cypress Semiconductor Corp.
CY7C09569V 's PackagesCY7C09569V 's pdf datasheet
CY7C09569V-100AC
CY7C09569V-100AXC
CY7C09569V-100BBC
CY7C09569V-83AC
CY7C09569V-83AXC
CY7C09569V-83BBC
CY7C09569V-67AC
CY7C09569V-67BBC
CY7C09579V-100AC
CY7C09579V-100AXC
CY7C09579V-100BBC
CY7C09579V-83AC
CY7C09579V-83AXC
CY7C09579V-83AI
CY7C09579V-83AXI
CY7C09579V-83BBC
CY7C09579V-83BBI
CY7C09579V-67AC
CY7C09579V-67BBC
CY7C09579V




CY7C09569V Pinout, Pinouts
CY7C09569V pinout,Pin out
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