1-Mbit (32K X 32) Pipelined Sync SRAM

The CY7C1215H SRAM integrates 32K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit Counter for internal burst operation. All synchronous inputs are gated by Registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE ), depth-expansion Chip Enables (CE and CE ), Burst 1 2 3 Control inputs (ADSC, ADSP, and ADV), Write Enables (BW , and BWE), and Global Write (GW). Asynchronous [A:D] inputs include the Output Enable (OE) and the ZZ pin. By Cypress Semiconductor Corp.
CY7C1215H 's PackagesCY7C1215H 's pdf datasheet

CY7C1215H Pinout, Pinouts
CY7C1215H pinout,Pin out
This is one package pinout of CY7C1215H,If you need more pinouts please download CY7C1215H's pdf datasheet.

CY7C1215H circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

Related Electronics Part Number

Related Keywords:

CY7C1215H Pb-Free CY7C1215H Cross Reference CY7C1215H Schematic CY7C1215H Distributor
CY7C1215H Application Notes CY7C1215H RoHS CY7C1215H Circuits CY7C1215H footprint
Hot categories