2-Mbit (128K X 18) Pipelined DCD Sync SRAM

The CY7C1223H SRAM integrates 128K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit Counter for internal burst operation. All synchronous inputs are gated by Registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE ), depth-expansion Chip Enables (CE and CE ), Burst 1 2 3 Control inputs (ADSC, ADSP, and ADV), Write Enables (BW and BWE), and Global Write (GW). Asynchronous [A:B] inputs include the Output Enable (OE) and the ZZ pin. By Cypress Semiconductor Corp.
CY7C1223H 's PackagesCY7C1223H 's pdf datasheet

CY7C1223H Pinout, Pinouts
CY7C1223H pinout,Pin out
This is one package pinout of CY7C1223H,If you need more pinouts please download CY7C1223H's pdf datasheet.

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