2-Mbit (128K X 18) Flow-Through SRAM With NoBL? Architecture

The CY7C1231H is a 3.3V/2.5V, 128K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1231H is equipped with the advanced No Bus Latency, (NoBL,) Logic required to enable consecutive Read/Write operations with data being transferred on every Clock cycle. This feature dramatically improves the throughput of data through the SRAM especially in systems that require frequent Write-Read transitions. By Cypress Semiconductor Corp.