2-Mbit (128K X 18) Flow-Through SRAM With NoBL? Architecture

The CY7C1231H is a 3.3V/2.5V, 128K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1231H is equipped with the advanced No Bus Latency, (NoBL,) Logic required to enable consecutive Read/Write operations with data being transferred on every Clock cycle. This feature dramatically improves the throughput of data through the SRAM especially in systems that require frequent Write-Read transitions. By Cypress Semiconductor Corp.
CY7C1231H 's PackagesCY7C1231H 's pdf datasheet

CY7C1231H Pinout, Pinouts
CY7C1231H pinout,Pin out
This is one package pinout of CY7C1231H,If you need more pinouts please download CY7C1231H's pdf datasheet.

CY7C1231H circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

Related Electronics Part Number

Related Keywords:

CY7C1231H Pb-Free CY7C1231H Cross Reference CY7C1231H Schematic CY7C1231H Distributor
CY7C1231H Application Notes CY7C1231H RoHS CY7C1231H Circuits CY7C1231H footprint
Hot categories