9-Mbit QDR- II? SRAM 2-Word Burst Architecture

The CY7C1292DV18 and CY7C1294DV18 are 1.8V Synchronous Pipelined SRAMs equipped with QDR,-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write opera- tions. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to turn-around t data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K Clock and the Write address is latched on the rising edge of the K Clock Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) Interfaces Each address location is associated with two 18-bit words CY7C1292DV18 or 36-bit words CY7C1294DV18 that burst sequentially into or out of the device. Since data CAN be transferred into and out of the device on every rising edge of both input Clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus turn-arounds. By Cypress Semiconductor Corp.
CY7C1294DV18 's PackagesCY7C1294DV18 's pdf datasheet
CY7C1292DV18-167BZC
CY7C1294DV18-167BZC
CY7C1292DV18-167BZXC
CY7C1294DV18-167BZXC
CY7C1292DV18-167BZI
CY7C1294DV18-167BZI
CY7C1292DV18-167BZXI
CY7C1294DV18-167BZXI
CY7C1292DV18-200BZC
CY7C1294DV18-200BZC
CY7C1292DV18-200BZXC
CY7C1294DV18-200BZXC
CY7C1292DV18-200BZI
CY7C1294DV18-200BZI
CY7C1292DV18-200BZXI
CY7C1294DV18-200BZXI
CY7C1292DV18-250BZC
CY7C1294DV18-250BZC
CY7C1292DV18-250BZXC
CY7C1294DV18-250BZXC
CY7C1292DV18-250BZI
CY7C1294DV18-250BZI
CY7C1292DV18-250BZXI
CY7C1294DV18-250BZXI
CY7C1292DV18




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