18-Mbit Burst Of 2 Pipelined SRAM With QDR? Architecture

The CY7C1303BV25 and CY7C1306BV25 are 2.5V Synchronous Pipelined SRAMs equipped with QDR, archi- tecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data inputs to support Write operations. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K Clock and the Write address is latched on the rising edge of K Clock QDR has separate data inputs and data outputs to completely eliminate the need to turn-around the data bus required wi common I/O devices. Accesses to the CY7C1303BV25 CY7C1306BV25 Read and Write ports are completely independent of one another. All accesses are initiated synchronously on the rising edge of the positive input Clock (K). In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) inter- faces. Therefore, data CAN be transferred into the device on every rising edge of both input Clocks (K and K) and out of the device on every rising edge of the output Clock (C and C, or K and K when in single Clock mode) thereby maximizing perfor- mance while simplifying system design. Each address location is associated with two 18-bit words CY7C1303BV25 or two 36-bit words CY7C1306BV25 that burst sequentially into or out of the device. By Cypress Semiconductor Corp.
CY7C1303BV25 's PackagesCY7C1303BV25 's pdf datasheet
CY7C1303BV25-167BZC
CY7C1306BV25-167BZC
CY7C1303BV25-167BZXC
CY7C1306BV25-167BZXC
CY7C1303BV25-167BZI
CY7C1306BV25-167BZI
CY7C1303BV25-167BZXI
CY7C1306BV25-167BZXI
CY7C1306BV25




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CY7C1303BV25 Application circuits
CY7C1303BV25 circuits
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