2-Mbit (128K X 18) Pipelined Sync SRAM

The CY7C1326H SRAM integrates 128K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit Counter for internal burst operation. All synchronous inputs are gated by Registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE ), depth-expansion Chip Enables (CE and CE ), Burst 1 2 3 Control inputs (ADSC, ADSP, and ADV), Write Enables (BW and BWE), and Global Write (GW). Asynchronous [A:B] inputs include the Output Enable (OE) and the ZZ pin. By Cypress Semiconductor Corp.