4-Mbit (256K X 18) Pipelined DCD Sync SRAM
The CY7C1328G SRAM integrates 256K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit Counter for internal burst operation. All synchronous inputs are gated by Registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE ), depth-expansion Chip Enables (CE and CE ), Burst 1 2 3 Control inputs (ADSC, ADSP, ADV), Write Enables and (BW , and BWE), and Global Write (GW). Asynchronous [A:B] inputs include the Output Enable (OE) and the ZZ pin. By Cypress Semiconductor Corp.
|CY7C1328G-133AXIT||Cypress Semiconductor||4-Mbit (256K x 18) Pipelined DCD Sync SRAM; Architecture: Standard Sync, Pipeline DCD; Density: 4 Mb; Organization: 256Kb x 18; Vcc (V): 3.1 to 3.6 V|
|CY7C1328G-133AXI||Cypress Semiconductor||IC 256K X 18 CACHE SRAM, 4 ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100, Static RAM|
|CY7C1328G Pb-Free||CY7C1328G Cross Reference||CY7C1328G Schematic||CY7C1328G Distributor|
|CY7C1328G Application Notes||CY7C1328G RoHS||CY7C1328G Circuits||CY7C1328G footprint|