2-Mbit (64K X 32) Pipelined Sync SRAM

The CY7C1329H SRAM integrates 64K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit Counter for internal burst operation. All synchronous inputs are gated by Registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE ), depth-expansion Chip Enables (CE and CE ), Burst 1 2 3 Control inputs (ADSC, ADSP, and ADV), Write Enables (BW and BWE), and Global Write (GW). Asynchronous [A:D] inputs include the Output Enable (OE) and the ZZ pin. By Cypress Semiconductor Corp.
CY7C1329H 's PackagesCY7C1329H 's pdf datasheet

CY7C1329H Pinout, Pinouts
CY7C1329H pinout,Pin out
This is one package pinout of CY7C1329H,If you need more pinouts please download CY7C1329H's pdf datasheet.

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