2-Mbit (64K X 32) Pipelined SRAM With NoBL? Architecture

The CY7C1334H is a 3.3V/2.5V, 64K x 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1334H is equipped with the advanced No Bus Latency, (NoBL,) Logic required to enable consecutive Read/Write operations with data being transferred on every Clock cycle. This feature dramatically improves the throughput of the SRAM especially in systems that require frequent Write/Read transitions. By Cypress Semiconductor Corp.