2-Mbit (64K X 32) Pipelined SRAM With NoBL? Architecture

The CY7C1334H is a 3.3V/2.5V, 64K x 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1334H is equipped with the advanced No Bus Latency, (NoBL,) Logic required to enable consecutive Read/Write operations with data being transferred on every Clock cycle. This feature dramatically improves the throughput of the SRAM especially in systems that require frequent Write/Read transitions. By Cypress Semiconductor Corp.
CY7C1334H 's PackagesCY7C1334H 's pdf datasheet
CY7C1334H-166AXC
CY7C1334H-166AXI
CY7C1334H-133AXC
CY7C1334H-133AXI

CY7C1334H pdf datasheet download


CY7C1334H Pinout, Pinouts
CY7C1334H pinout,Pin out
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