2-Mbit (64K X 32) Flow-Through Sync SRAM

The CY7C1336H is a 64K x 32 synchronous cache RAM designed to Interface with high-speed Microprocessors with minimum glue Logic Maximum access delay from Clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip Counter captures the first address in a burst and increments the address automati- cally for the rest of the burst access. All synchronous inputs are gated by Registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, ADV), Write Enables and (BW , and BWE), and Global Write (GW). Asynchronous [A:D] inputs include the Output Enable (OE) and the ZZ pin. By Cypress Semiconductor Corp.
CY7C1336H 's PackagesCY7C1336H 's pdf datasheet
CY7C1336H-133AXC
CY7C1336H-133AXI
CY7C1336H-100AXC
CY7C1336H-100AXI




CY7C1336H Pinout, Pinouts
CY7C1336H pinout,Pin out
This is one package pinout of CY7C1336H,If you need more pinouts please download CY7C1336H's pdf datasheet.

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