4-Mbit (128K X 32) Flow-Through Sync SRAM

The CY7C1338G is a 128K x 32 synchronous cache RAM designed to Interface with high-speed Microprocessors with minimum glue Logic Maximum access delay from Clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip Counter captures the first address in a burst and increments the address automati- cally for the rest of the burst access. All synchronous inputs are gated by Registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE ), depth-expansion Chip Enables (CE and CE ), Burst 1 2 3 Control inputs (ADSC, ADSP, and ADV), Write Enables (BW , and BWE), and Global Write (GW). Asynchronous [A:D] inputs include the Output Enable (OE) and the ZZ pin. By Cypress Semiconductor Corp.
CY7C1338G 's PackagesCY7C1338G 's pdf datasheet
CY7C1338G-133AXC
CY7C1338G-133BGC
CY7C1338G-133BGXC
CY7C1338G-133AXI
CY7C1338G-133BGI
CY7C1338G-133BGXI
CY7C1338G-100AXC
CY7C1338G-100BGC
CY7C1338G-100BGXC
CY7C1338G-100AXI
CY7C1338G-100BGI
CY7C1338G-100BGXI




CY7C1338G Pinout, Pinouts
CY7C1338G pinout,Pin out
This is one package pinout of CY7C1338G,If you need more pinouts please download CY7C1338G's pdf datasheet.

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