2-Mbit (64K X 36) Pipelined Sync SRAM

The CY7C1346H SRAM integrates 64K x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit Counter for internal burst operation. All synchronous inputs are gated by Registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable ( ), depth-expansion Chip Enables (CE and ), Burst CE 2 CE 1 3 Control inputs ( , , ), Write Enables ADSC ADSP and ADV ( , and ), and Global Write (GW). Asynchronous BW[A:D] BWE inputs include the Output Enable (OE) and the ZZ pin. By Cypress Semiconductor Corp.
CY7C1346H 's PackagesCY7C1346H 's pdf datasheet

CY7C1346H Pinout, Pinouts
CY7C1346H pinout,Pin out
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