4-Mbit (128K X 36) Pipelined Sync SRAMThe CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined
SRAM designed to support zero-wait-state secondary cache
with minimal glue Logic CY7C1347G IO pins CAN operate at
either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant
when V = 2.5V. All synchronous inputs pass through input
DDQ
Registers controlled by the rising edge of the Clock All data
outputs pass through output Registers controlled by the rising
edge of the Clock Maximum access delay from the Clock rise
is 2.6 ns (250 MHz device). CY7C1347G supports either the
interleaved burst sequence used by the Intel Pentium
processor or a linear burst sequence used by processors such
,
as the PowerPC . The burst sequence is selected through the
MODE pin. Accesses CAN be initiated by asserting either the
Address Strobe from Processor (ADSP) or the Address Strobe
from Controller (ADSC) at Clock rise. Address advancement
through the burst sequence is controlled by the ADV input. A
2-bit on-chip wraparound burst Counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access. By Cypress Semiconductor Corp.
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