4-Mbit (128K X 36) Pipelined Sync SRAM

The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue Logic CY7C1347G IO pins CAN operate at either the 2.5V or the 3.3V level; the IO pins are 3.3V tolerant when V = 2.5V. All synchronous inputs pass through input DDQ Registers controlled by the rising edge of the Clock All data outputs pass through output Registers controlled by the rising edge of the Clock Maximum access delay from the Clock rise is 2.6 ns (250 MHz device). CY7C1347G supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such , as the PowerPC . The burst sequence is selected through the MODE pin. Accesses CAN be initiated by asserting either the Address Strobe from Processor (ADSP) or the Address Strobe from Controller (ADSC) at Clock rise. Address advancement through the burst sequence is controlled by the ADV input. A 2-bit on-chip wraparound burst Counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. By Cypress Semiconductor Corp.
CY7C1347G 's PackagesCY7C1347G 's pdf datasheet
CY7C1347G-133AXC
CY7C1347G-133BGC
CY7C1347G-133BGX
CY7C1347G-133BZC
CY7C1347G-133BZXC
CY7C1347G-133AXI
CY7C1347G-133BGI
CY7C1347G-133BGXI
CY7C1347G-133BZI
CY7C1347G-133BZXI
CY7C1347G-166AXC
CY7C1347G-166BGC
CY7C1347G-166BGX
CY7C1347G-166BZC
CY7C1347G-166BZXC
CY7C1347G-166AXI
CY7C1347G-166BGI
CY7C1347G-166BGXI
CY7C1347G-166BZI
CY7C1347G-166BZXI
CY7C1347G-200AXC
CY7C1347G-200BGC
CY7C1347G-200BGX
CY7C1347G-200BZC
CY7C1347G-200BZXC
CY7C1347G-200AXI
CY7C1347G-200BGI
CY7C1347G-200BGXI
CY7C1347G-200BZI
CY7C1347G-200BZXI
CY7C1347G-250AXC
CY7C1347G-250BGC
CY7C1347G-250BGX
CY7C1347G-250BZC
CY7C1347G-250BZXC
CY7C1347G-250AXI
CY7C1347G-250BGI
CY7C1347G-250BGXI
CY7C1347G-250BZI
CY7C1347G-250BZXI




CY7C1347G Pinout, Pinouts
CY7C1347G pinout,Pin out
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