4-Mbit (128K X 36) Flow-through SRAM With NoBL? Architecture
The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency, (NoBL,) Logic required to enable consecutive Read/Write operations with data being transferred on every Clock cycle. This feature dramatically improves the throughput of data through the SRAM especially in systems that require frequent Write-Read transitions. By Cypress Semiconductor Corp.
|CY7C1351G-100AXC||Cypress Semiconductor||IC 128K X 36 ZBT SRAM, 8 ns, PQFP100, 20 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100, Static RAM|
|CY7C1351G-100AXCT||Cypress Semiconductor||IC IC,SYNC SRAM,128KX36,CMOS,QFP,100PIN,PLASTIC, Static RAM|
|CY7C1351G-133AXC||Cypress Semiconductor||IC 128K X 36 ZBT SRAM, 6.5 ns, PQFP100, 20 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, TQFP-100, Static RAM|
|CY7C1351G Pb-Free||CY7C1351G Cross Reference||CY7C1351G Schematic||CY7C1351G Distributor|
|CY7C1351G Application Notes||CY7C1351G RoHS||CY7C1351G Circuits||CY7C1351G footprint|