256k X18 Pipelined Sram With Nobl Architecture

The CY7C1352 is a 3.3V 256K by 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352 is equipped with the advanced No Bus Latency (NoBL) Logic required to enable consecutive Read/Write operations with data being transferred on every Clock cycle. This feature dramatically improves the throughput of the SRAM especially in systems that require frequent Read/Write transitions.The CY7C1352 is pin/functionally com- patible to ZBT SRAMs MCM63Z819 and MT55L256L18P. By Cypress Semiconductor Corp.
CY7C1352 's PackagesCY7C1352 's pdf datasheet



CY7C1352 Pinout, Pinouts
CY7C1352 pinout,Pin out
This is one package pinout of CY7C1352,If you need more pinouts please download CY7C1352's pdf datasheet.

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