4-Mbit (256K X 18) Pipelined SRAM With NoBL? Architecture

The CY7C1352G is a 3.3V, 256K x 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352G is equipped with the advanced No Bus Latency, (NoBL,) Logic required to enable consec- utive Read/Write operations with data being transferred on every Clock cycle. This feature dramatically improves the throughput of the SRAM especially in systems that require frequent Write/Read transitions. By Cypress Semiconductor Corp.
CY7C1352G 's PackagesCY7C1352G 's pdf datasheet

CY7C1352G Pinout, Pinouts
CY7C1352G pinout,Pin out
This is one package pinout of CY7C1352G,If you need more pinouts please download CY7C1352G's pdf datasheet.

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