256k X 36/512k X 18 Synchronous Flow-thru Sram With Nobl Architecture

The CY7C1355A and CY7C1357A SRAMs are designed to eliminate dead cycles when transitions from READ to WRITE or vice versa. These SRAMs are optimized for 100 percent bus utilization and achieves Zero Bus Latency (ZBL). They integrate 262,144 36 and 524,288 18 SRAM cells, respec- tively, with advanced synchronous peripheral circuitry and a 2-bit Counter for internal burst operation. These employ high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of Six Transistors The CY7C1355A and CY7C1357A have an on-chip 2-bit burst Counter In the burst mode, the CY7C1355A and CY7C1357A provide four cycles of data for a single address presented to the SRAM The order of the burst sequence is defined by the MODE input pin. The MODE pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address (ADV/LD = LOW) or increment the internal burst Counter (ADV/LD = HIGH) By Cypress Semiconductor Corp.
CY7C1355A 's PackagesCY7C1355A 's pdf datasheet

CY7C1355A Pinout, Pinouts
CY7C1355A pinout,Pin out
This is one package pinout of CY7C1355A,If you need more pinouts please download CY7C1355A's pdf datasheet.

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