9-Mbit (256K X 32) Pipelined Sync SRAMThe CY7C1364C SRAM integrates 256K x 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
Counter for internal burst operation. All synchronous inputs are
gated by Registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
[2]
(CE ), depth-expansion Chip Enables (CE and CE ), Burst
1 2 3
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW , and BWE), and Global Write (GW). Asynchronous
[A:D]
inputs include the Output Enable (OE) and the ZZ pin. By Cypress Semiconductor Corp.
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CY7C1364C Pb-Free | CY7C1364C Cross Reference | CY7C1364C Schematic | CY7C1364C Distributor |
CY7C1364C Application Notes | CY7C1364C RoHS | CY7C1364C Circuits | CY7C1364C footprint |