9-Mbit (256K X 32) Flow-Through Sync SRAMThe CY7C1365C is a 256K x 32 synchronous cache RAM
designed to Interface with high-speed Microprocessors with
minimum glue Logic Maximum access delay from Clock rise is
6.5 ns (133-MHz version). A 2-bit on-chip Counter captures the
first address in a burst and increments the address automati-
cally for the rest of the burst access. All synchronous inputs
are gated by Registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
[2]
(CE1), depth-expansion Chip Enables (CE2 and CE3 ), Burst
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW[A:D], and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin. By Cypress Semiconductor Corp.
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