9-Mbit (256K X 32) Flow-Through Sync SRAM

The CY7C1365C is a 256K x 32 synchronous cache RAM designed to Interface with high-speed Microprocessors with minimum glue Logic Maximum access delay from Clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip Counter captures the first address in a burst and increments the address automati- cally for the rest of the burst access. All synchronous inputs are gated by Registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable [2] (CE1), depth-expansion Chip Enables (CE2 and CE3 ), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:D], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. By Cypress Semiconductor Corp.
CY7C1365C 's PackagesCY7C1365C 's pdf datasheet

CY7C1365C Pinout, Pinouts
CY7C1365C pinout,Pin out
This is one package pinout of CY7C1365C,If you need more pinouts please download CY7C1365C's pdf datasheet.

CY7C1365C circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

Related Electronics Part Number

Related Keywords:

CY7C1365C Pb-Free CY7C1365C Cross Reference CY7C1365C Schematic CY7C1365C Distributor
CY7C1365C Application Notes CY7C1365C RoHS CY7C1365C Circuits CY7C1365C footprint
Hot categories