9-Mbit (256K X 36/512K X 18) Pipelined DCD Sync SRAM

The CY7C1366C CY7C1367C SRAM integrates 256K x 36 and 512K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit Counter for internal burst operation. All synchronous inputs are gated by Registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE ), depth-expansion Chip 1 [2] Enables (CE and CE ), Burst Control inputs (ADSC, ADSP, 2 3 ADV), Write Enables (BW , and BWE), and Global Write and X (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. By Cypress Semiconductor Corp.
CY7C1367C 's PackagesCY7C1367C 's pdf datasheet
CY7C1366C-166AXC
CY7C1367C-166AXC
CY7C1366C-166BGC
CY7C1367C-166BGC
CY7C1366C-166BGXC
CY7C1367C-166BGXC
CY7C1366C-166BZC
CY7C1367C-166BZC
CY7C1366C-166BZXC
CY7C1367C-166BZXC
CY7C1366C-166AXI
CY7C1367C-166AXI
CY7C1366C-166BGI
CY7C1367C-166BGI
CY7C1366C-166BGXI
CY7C1367C-166BGXI
CY7C1366C-166BZI
CY7C1367C-166BZI
CY7C1366C-166BZXI
CY7C1367C-166BZXI
CY7C1366C-200AXC
CY7C1367C-200AXC
CY7C1366C-200BGC
CY7C1367C-200BGC
CY7C1366C-200BGXC
CY7C1367C-200BGXC
CY7C1366C-200BZC
CY7C1367C-200BZC
CY7C1366C-200BZXC
CY7C1367C-200BZXC
CY7C1366C-200AXI
CY7C1367C-200AXI
CY7C1366C-200BGI
CY7C1367C-200BGI
CY7C1366C-200BGXI
CY7C1367C-200BGXI
CY7C1366C-200BZI
CY7C1367C-200BZI
CY7C1366C-200BZXI
CY7C1367C-200BZXI
CY7C1366C-250AXC
CY7C1367C-250AXC
CY7C1366C-250BGC
CY7C1367C-250BGC
CY7C1366C-250BGXC
CY7C1367C-250BGXC
CY7C1366C-250BZC
CY7C1367C-250BZC
CY7C1366C-250BZXC
CY7C1367C-250BZXC
CY7C1366C-250AXI
CY7C1367C-250AXI
CY7C1366C-250BGI
CY7C1367C-250BGI
CY7C1366C-250BGXI
CY7C1367C-250BGXI
CY7C1366C-250BZI
CY7C1367C-250BZI
CY7C1366C-250BZXI
CY7C1367C-250BZXI
CY7C1366C




CY7C1367C Pinout, Pinouts
CY7C1367C pinout,Pin out
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