• Product pinout
  • Description
  • SN65LVDS104,1:4 LVDS Clock Fanout Buffer
  • The SN65LVDS104 and SN65LVDS105 are a differential line receiver and a LVTTL input (respectively) connected to four differential line drivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in ...
  • SN65LVDS105,1 LVTTL:4 LVDS Clock Fanout Buffer
  • The SN65LVDS104 and SN65LVDS105 are a differential line receiver and a LVTTL input (respectively) connected to four differential line drivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in ...
  • SN65LVDS1050,2.7V Dual LVDS Transmitter/Receiver
  • The SN65LVDS1050 is similar to the SN65LVDS050 except that it is characterized for operation with a lower supply voltage range and packaged in the thin shrink outline package for portable battery-powered applications.
    The differential line drivers and ...
  • SN65LVDS108,1:8 LVDS Clock Fanout Buffer
  • The SN65LVDS108 is configured as one differential line receiver connected to eight differential line drivers. Individual output enables are provided for each output and an additional enable is provided for all outputs.
    The line receivers and line drivers ...
  • CDC5806,6 Output PLL Frequency Generator
  • The CDC5806 is a clock generator which synthesizes video clocks, audio clocks, CPU clock, ASIC clock, USB clock, and a memory card clock from a 54-MHz system clock.
    Three phase-locked loops (PLLs) are used to generate the different frequencies from the ...
  • CDC857-2,Phase-Lock Loop Clock Drivers
  • The CDC857-2 and CDC857-3 are high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. They use a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. The CDC857-3 operates at 3.3 ...
  • CDC857-3,Phase-Lock Loop Clock Drivers
  • The CDC857-2 and CDC857-3 are high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. They use a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. The CDC857-3 operates at 3.3 ...
  • CDCV855,1:4 DDR PLL Clock Driver
  • The CDCV855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to four differential pairs of clock outputs (Y[0:3], Y[0:3]) and one differential pair of feedback clock outputs (FBOUT, ...
  • CDCV857,1:10 DDR Phase-Lock Loop Clock Driver
  • The CDCV857 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback clock output (FBOUT, FBOUT). ...
  • CDCV857B,2.5 V Phase Lock Loop DDR Clock Driver
  • The CDCV857B is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to 10 differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback clock outputs (FBOUT, ...
  • CDC2351,1-Line To 10-Line Clock Driver With 3-State Outputs
  • The CDC2351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with minimum skew for clock distribution. The output-enable (OE) input disables the outputs to a high-impedance state. Each output has an internal series ...
  • CDC2509,3.3-V Phase-Lock Loop Clock Driver With 3-State Outputs
  • The CDC2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. They use a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. They are specifically designed for use ...
  • CDC2509B,1-to-9 PLL Clock Driver
  • The CDC2509B is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock drivers. They use a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. They are specifically designed for use ...
  • CDC2509C,1-to-9 PLL Clock Driver
  • The CDC2509C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with ...
  • CDC2510,3.3-V Phase-Lock Loop Clock Driver
  • The CDC2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with ...
  • CDC2510A,3.3-V Phase-Lock Loop Clock Driver
  • The CDC2510A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with ...
  • CDC2510B,3.3-V Phase-Lock Loop Clock Driver
  • The CDC2510B is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with ...
  • CDC2510C,3.3-V Phase-Lock Loop Clock Driver
  • The CDC2510C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with ...
  • CDC2516,3.3-V Phase-Lock Loop Clock Driver With 3-State Outputs
  • The CDC2516 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback output (FBOUT) to the clock (CLK) input signal. It is specifically designed for use with ...
  • CDC328A,1-To-6 Clock Driver With Selectable Polarity
  • The CDC328A contains a clock-driver circuit that distributes one input signal to six outputs with minimum skew for clock distribution. Through the use of the polarity-control inputs (T/C), various combinations of true and complementary outputs can be ...
  • CDC329A,1-To-6 Clock Driver With Selectable Polarity
  • The CDC329A contains a clock-driver circuit that distributes one input signal to six outputs with minimum skew for clock distribution. Through the use of the polarity-control inputs (T/C), various combinations of true and complementary outputs can be ...
  • CDC340,1-to-8 Clock Driver With Tight AC Specification
  • The CDC340 is a high-performance clock-driver circuit that distributes one (A) input signal to eight (Y) outputs with minimum skew for clock distribution. Through the use of the control pins (1G and 2G), the outputs can be placed in a high state regardless of ...
  • CDC341,1-to-8 Clock Driver With Tight AC Specification
  • The CDC341 is a high-performance clock-driver circuit that distributes one (A) input signal to eight (Y) outputs with minimum skew for clock distribution. Through the use of the control pins (1G and 2G), the outputs can be placed in a low state regardless of ...
  • CDC391,1-To-6 Clock Driver With Selectable Polarity
  • The CDC391 contains a clock-driver circuit that distributes one input signal to six outputs with minimum skew for clock distribution. Through the use of the polarity-control (T/C) inputs, various combinations of true and complementary outputs can be obtained. ...
  • CDC509,3.3V Phase Lock Loop Clock Driver
  • The CDC509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with ...
  • CDC516,3.3V Phase Lock Loop Clock Driver With 3-State Outputs
  • The CDC516 is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback output (FBOUT) to the clock (CLK) input signal. It is specifically designed for ...
  • CDCF2509,3.3-V Phase-Lock Loop Clock Driver
  • The CDCF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with ...
  • CDCF2510,3.3-V Phase-Lock Loop Clock Driver
  • The CDCF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with ...
  • CDCVF25081,1:8 3.3-V Phase Lock Loop Clock Driver
  • The CDCVF25081 is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks to the input clock signal. The CDCVF25081 operates from a nominal supply voltage of 3.3 ...
  • CDCVF2509,3.3-V Phase-Lock Loop Clock Driver
  • The CDCVF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with ...
  • CDCVF2509A,3.3-V Phase-Lock Look Clock Driver With Power Down
  • The CDCVF2509A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with ...
  • CDCVF2510,3.3-V Phase-Lock Loop Clock Driver
  • The CDCVF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically ...
  • CDC111,3.3V LVPECL Differential Clock Driver
  • The differential LVPECL clock-driver circuit distributes one pair of differential LVPECL clock inputs (CLKIN, CLKIN) to nine pairs of differential clock (Y, Y) outputs with minimum skew for clock distribution. It is specifically designed for driving 50- ...
  • CDCLVP110,1:10 LVPECL/HSTL To LVPECL Clock Driver
  • The CDCLVP110 clock driver distributes one differential clock pair of either LVPECL or HSTL (selectable) input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP110 can accept two clock ...
  • CDCP1803,1:3 LVPECL Clock Buffer With Programable Divider
  • The CDCP1803 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y[2:0] and Y[2:0] with minimum skew for clock distribution. The CDCP1803 is specifically designed for driving 50- transmission ...
  • CDCVF111,1:9 Differential LVPECL Clock Driver
  • The differential LVPECL clock-driver circuit distributes one pair of differential LVPECL clock inputs (CLKIN, CLKIN) to nine pairs of differential clock (Y, Y) outputs with minimum skew for clock distribution. It is specifically designed for driving 50- ...
  • CDC203,3.3V 6-Bit Inverter/Clock Driver
  • The CDC203 contains six independent inverters. The device performs the Boolean function Y = A. It is designed specifically for applications requiring low skew between switching outputs.
    The CDC203 is characterized for operation from 25?C to 70?C.
    ...
  • CDC204,5V 6-Bit Inverter / Clock Driver
  • The CDC204 contains six independent inverters. The device performs the Boolean function Y = A. It is designed specifically for applications requiring low skew between switching outputs.
    The CDC204 is characterized for operation from TA = 25C to 70C.
  • CDC208,5V Dual 1-to-4 Clock Driver
  • The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew for clock distribution (see Figure 2). The device also offers two output-enable (OE1 and OE2) inputs for each circuit that can force the outputs to be ...
  • CDC303,1-To-8, Divide-By-2 Clock Driver With Preset And Clear
  • The CDC303 contains eight flip-flops designed to have low skew between outputs. The eight outputs (six in-phase with CLK and two out-of-phase) toggle on successive CLK pulses. Preset () and clear () inputs are provided to set the Q and Q outputs high or low ...
  • CDCE401,Oscillator IC With Electronic Calibration
  • The CDCE401 is designed to achieve today?s demanding challenges for crystal oscillator modules. The small form factor of the unpackaged die or the QFN package reduces the space consumption of the device to the technical minimum level of today?s silicon ...
  • CDCV304,General Purpose And PCI-X 1:4 Clock Buffer
  • The CDCV304 is a high-performance, low-skew, general-purpose and PCI-X clock buffer. It distributes one input clock signal (CLKIN) to the output clocks (1Y[0:3]). It is specifically designed for use with PCI-X applications. The CDCV304 operates at 3.3 V.
  • LMV112,40 MHz Dual Clock Buffer
  • The LMV112 is a high speed dual clock buffer designed for portable communications and accurate multi-clock systems. The LMV112 integrates two 40 MHz low noise buffers which optimizes application and out performs large discrete solutions. This device enables ...
  • LMV115,GSM Baseband 30MHz 2.8V Oscillator Buffer
  • The LMV115 is a 30MHz buffer specially designed to minimize the effects of spurious signals from the base band chip to the oscillator. The buffer also minimizes the influence of varying load resistance and capacitance to the oscillator and increases the drive ...
  • DS92CK16,3V BLVDS 1 To 6 Clock Buffer/Bus Transceiver
  • The DS92CK16 1 to 6 Clock Buffer/Bus Transceiver is a one to six CMOS differential clock distribution device utilizing Bus Low Voltage Differential Signaling (BLVDS) technology. This clock distribution device is designed for applications requiring ultra low ...
  • ADCLK905,Ultrafast SiGe ECL Clock/Data Buffers
  • The ADCLK905 (one input, one output), ADCLK907 (dual one input, one output), and ADCLK925 (one input, two outputs) are ultrafast clock/data buffers fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process.
    The ...
  • ADCLK907,Ultrafast SiGe ECL Clock/Data Buffers
  • The ADCLK905 (one input, one output), ADCLK907 (dual one input, one output), and ADCLK925 (one input, two outputs) are ultrafast clock/data buffers fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process.
    The ...
  • ADCLK925,Ultrafast SiGe ECL Clock/Data Buffers
  • The ADCLK905 (one input, one output), ADCLK907 (dual one input, one output), and ADCLK925 (one input, two outputs) are ultrafast clock/data buffers fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process.
    The ...
  • 82C84A,CMOS Clock Generator Driver
  • The Intersil 82C84A is a high performance CMOS Clock Generator driver which is designed to service the requirements of both CMOS and NMOS microprocessors such as the 80C86, 80C88, 8086 and the 8088. The chip contains a crystal controlled oscillator, a ...
  • PCK2001M,PCK2001M 14.318-150 MHz I²C 1:10 Clock Buffer
  • The PCK2001M is a 1-10 fanout buffer used for 133/100 MHz CPU, 66/33 MHz PCI, 14.318 MHz REF, or 133/100/66 MHz SDRAM clock distribution. 10 outputs are typically used to support up to 2 SDRAM DIMMs commonly found in laptop or mobile applications. The ...
  • PCK2001,PCK2001 14.318-150 MHz I2C 1:18 Clock Buffer
  • The PCK2001 is a 1-18 fanout buffer used for 133/100 MHz CPU, 66/33 MHz PCI, 14.318 MHz REF, or 133/100/66 MHz SDRAM clock distribution. 18 outputs are typically used to support up to four SDRAM DIMMS commonly found in desktop, workstation or ...
  • PCK2002M,PCK2002M 0-300 MHz I2C 1:10 Clock Buffer
  • The PCK2002M is a 1-10 fanout buffer used for 133/100 MHz CPU, 66/33 MHz PCI, 14.318 MHz REF, or 133/100/66 MHz SDRAM clock distribution. 10 outputs are typically used to support up to 2 SDRAM DIMMs commonly found in laptop or mobile applications. The ...
  • PCK2002PL,PCK2002PL 533 MHz PCI-X Clock Buffer
  • The PCK2002PL is a 1-4 fanout buffer used as a high-performance, low skew, general purpose and PCI-X clock buffer. It distributes one input clock (BUF_IN) signal to four output clocks (BUF_OUTn ).
    ...
  • PCK2002P,PCK2002P 533 MHz PCI-X Clock Buffer
  • The PCK2002PL is a 1- 4 fanout buffer used as a high-performance, low skew, general purpose and PCI-X clock buffer. It distributes one input clock (BUF_IN) signal to four output clocks (BUF_OUTn).
    ...
  • PCK2002,PCK2002 0-300 MHz I2C 1:18 Clock Buffer
  • The PCK2002 is a 1-18 fanout buffer used for 133/100 MHz CPU, 66/33 MHz PCI, 14.318 MHz REF, or 133/100/66 MHz SDRAM clock distribution. 18 outputs are typically used to support up to 4 SDRAM DIMMS commonly found in desktop, workstation or server ...
  • PCK2057,PCK2057 70-190 MHz I2C Differential 1:10 Clock Driver
  • The PCK2057 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs and one differential pair of feedback clock outputs. The clock outputs are ...