Introduction

Cyclic Redundancy Code (CRC) is commonly used to determine the correctness of a

data transmission or storage. This application note presents a solution to compute

16-bit and 32-bit CRCs on the ultra low-power TI MSP430 Microcontroller for the

bitwise algorithm (low memory, low cost) and the table-based algorithm (low MIPS, low

power). Both algorithms are presented in C and MSP430 assembly. Test code to verify

the implementations is also included.

The fundamental mathematics behind the CRC is polynomial division. An arbitrary message (a fixed block

of k information bits) is treated as if each bit were the binary coefficient of a polynomial of degree k-1.

Let ’ s assume that we augment that message by simply adding some arbitrary number of bits to the end of

the message which we will call the parity bits. If the original message is augmented such that the new

message (original message + parity bits), which we will refer to as the code word, is evenly divisible by a

known polynomial, which we will call the generator polynomial, then the receiver CAN assume that there

were no transmission errors. However, in practice, it is possible to introduce errors into the received

message that make detection of these errors impossible for a given generator polynomial. The generator

polynomial order and coefficients are related to how many errors it CAN detect, but this is beyond the

scope of this application note.

Many of today ’ s Communications protocols, such as HDLC and Ethernet use 16-bit and 32-bit CRCs,

respectively. The native implementation for computing and checking a CRC is bit-based which typically

makes hardware a more natural fit. However, any additional hardware CAN be preventative due to

increased cost, increased power, and increased board size. The MSP430 CAN do the bit-by-bit division

very well, however it is much more efficient at handling data in bytes or words. Fortunately, from the CRC

mathematics, a table-based solution has been developed that trades cycles for memory allowing a

processor to operate on bytes rather than bits. So now the designer CAN decide which resource is more

important: MIPS (power) or memory (cost). This app note presents the source code to compute 16-bit and

32-bit CRCs on the low power TI MSP430 Microprocessor for both the bit-by-bit algorithm and the

table-based algorithm. Both algorithms are supplied in C and MSP430 assembly. Projects and test code to

verify the CRC implementation is also included which CAN be run on an MSP430 (C and assembly code)

or a PC using Microsoft Visual C++ (C-code only).

Cyclic Redundancy Code (CRC) is commonly used to determine the correctness of a

data transmission or storage. This application note presents a solution to compute

16-bit and 32-bit CRCs on the ultra low-power TI MSP430 Microcontroller for the

bitwise algorithm (low memory, low cost) and the table-based algorithm (low MIPS, low

power). Both algorithms are presented in C and MSP430 assembly. Test code to verify

the implementations is also included.

The fundamental mathematics behind the CRC is polynomial division. An arbitrary message (a fixed block

of k information bits) is treated as if each bit were the binary coefficient of a polynomial of degree k-1.

Let ’ s assume that we augment that message by simply adding some arbitrary number of bits to the end of

the message which we will call the parity bits. If the original message is augmented such that the new

message (original message + parity bits), which we will refer to as the code word, is evenly divisible by a

known polynomial, which we will call the generator polynomial, then the receiver CAN assume that there

were no transmission errors. However, in practice, it is possible to introduce errors into the received

message that make detection of these errors impossible for a given generator polynomial. The generator

polynomial order and coefficients are related to how many errors it CAN detect, but this is beyond the

scope of this application note.

Many of today ’ s Communications protocols, such as HDLC and Ethernet use 16-bit and 32-bit CRCs,

respectively. The native implementation for computing and checking a CRC is bit-based which typically

makes hardware a more natural fit. However, any additional hardware CAN be preventative due to

increased cost, increased power, and increased board size. The MSP430 CAN do the bit-by-bit division

very well, however it is much more efficient at handling data in bytes or words. Fortunately, from the CRC

mathematics, a table-based solution has been developed that trades cycles for memory allowing a

processor to operate on bytes rather than bits. So now the designer CAN decide which resource is more

important: MIPS (power) or memory (cost). This app note presents the source code to compute 16-bit and

32-bit CRCs on the low power TI MSP430 Microprocessor for both the bit-by-bit algorithm and the

table-based algorithm. Both algorithms are supplied in C and MSP430 assembly. Projects and test code to

verify the CRC implementation is also included which CAN be run on an MSP430 (C and assembly code)

or a PC using Microsoft Visual C++ (C-code only).

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