Decoders/demultiplexers - National Semiconductor

These Schottky-clamped circuits 54LS138 DM54LS138 DM74LS138 54LS139 DM54LS139 DM74LS139 are designed to be used in high-performance memory-decoding or data-routing appli- cations, requiring very short propagation delay times. In high-performance memory systems these decoders CAN be used to minimize the effects of system decoding. When used with high-speed Memories the delay times of these decoders are usually less than the typical access time of the memory. This means that the effective system delay intro- duced by the decoder is negligible. The LS138 decodes one-of-eight lines, based upon the con- ditions at the three binary select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external Gates or inverters when ex- panding. A 24-line decoder CAN be implemented with no ex- ternal inverters, and a 32-line decoder requires only one inverter. An enable input CAN be used as a data input for demultiplexing applications. The LS139 comprises two separate two-line-to-four-line de- coders in a single package. The active-low enable input CAN be used as a data line in demultiplexing applications. All of these decoders/demultiplexers feature fully buffered inputs, presenting only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky Diodes to suppress line-ringing and simplify system design. By National Semiconductor Corporation
DM54LS138 's PackagesDM54LS138 's pdf datasheet

DM54LS138 Pinout, Pinouts
DM54LS138 pinout,Pin out
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