Dual J-K Positive-Edge-Triggered Flip-Flop

The DM74ALS109A is a dual edge-triggered Flip-Flop Each Flip-Flop has individual J, K, Clock clear and preset inputs, and also complementary Q and Q outputs. Information at input J or K is transferred to the Q output on the positive going edge of the Clock pulse. Clock triggering occurs at a voltage level of the Clock pulse and is not directly related to the transition time of the positive going pulse. When the Clock input is at either the HIGH or LOW level, the J, K input signal has no effect. Asynchronous preset and clear inputs will set or clear Q output respectively upon the application of low level signal. The J-K design allows operation as a D Flip-Flop by tying the J and K inputs together. By Fairchild Semiconductor
DM74ALS109A 's PackagesDM74ALS109A 's pdf datasheet

DM74ALS109A Pinout, Pinouts
DM74ALS109A pinout,Pin out
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