Octal 3-STATE Bus Transceiver And Register

This device DM74ALS652 incorporates an octal transceiver and an octal D-type Register configured to enable transmission of data from bus to bus or internal Register to bus.
This Bus Transceiver features totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high level Logic drive provide this device with the capability of being connected directly to and driving the bus lines in a bus organized system without need for Interface or pull-up components. They are particularly attractive for implementing Buffer Registers I/O ports, bidirectional bus drivers, and working Registers
The Registers in the DM74ALS652 are edge-triggered D-type Flip-Flops On the positive transition of the Clock (CAB or CBA), the input data is stored into the appropriate Register The CAB input controls the transfer of data into the A Register and the CBA input controls the B Register
The SAB and SBA control pins are provided to select whether real-time data or stored data is transferred. A LOW input level selects real-time data and a HIGH level selects stored data. The select controls have a "make before break" configuration to eliminate a glitch which would normally occur in a typical multiplexer during the transition between stored and real-time data.
The enable (GAB and G#BA) control pins provide four modes of operation: real-time data transfer from bus A to B, real-time data transfer from bus B to A, real-time bus A and/or B data transfer to internal storage, or internal stored data transfer to bus A and/or B.
By Fairchild Semiconductor
DM74ALS652 's PackagesDM74ALS652 's pdf datasheet

DM74ALS652 Pinout, Pinouts
DM74ALS652 pinout,Pin out
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