3-STATE Octal Buffer

These devices DM81LS95A provide eight, two-input Buffers in each package. All employ low-power-Schottky TTL technology. One of the two inputs to each Buffer is used as a control line to Gate the output into the high-impedance state, while the other input passes the data through the Buffer The DM81LS95A and DM81LS97A present true data at the out- puts, while the DM81LS96A is inverting. On the DM81LS95A and DM81LS96A versions, all eight 3-STATE enable lines are common, with access through a 2-input NOR Gate On the DM81LS97A version, four Buffers are enabled from one common line, and the other four Buffers are enabled form another common line. In all cases the outputs are placed in the 3-STATE condition by applying a high Logic level to the enable pins. By Fairchild Semiconductor
DM81LS95A 's PackagesDM81LS95A 's pdf datasheet
DM81LS95AWM SOIC
DM81LS95AN PDIP
DM81LS96AWM SOIC
DM81LS96AN PDIP
DM81LS97AN PDIP




DM81LS95A Pinout, Pinouts
DM81LS95A pinout,Pin out
This is one package pinout of DM81LS95A,If you need more pinouts please download DM81LS95A's pdf datasheet.

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