Microcmos Programmable 256k/1m/4m Dynamic Ram Controller/drivers

The DP8420A DP8421A DP8422A dynamic RAM controllers provide a low cost, single chip Interface between dynamic RAM and all 8-, 16- and 32-bit systems. The DP8420A DP8421A DP8422A gen- erate all the required access control signal Timing for DRAMs An on-chip refresh request Clock is used to auto- matically refresh the DRAM array. Refreshes and accesses are arbitrated on chip. If necessary, a WAIT or DTACK out- put inserts wait states into system access cycles, including burst mode accesses. RAS low time during refreshes and RAS precharge time after refreshes and back to back ac- cesses are guaranteed through the insertion of wait states. Separate on-chip precharge Counters for each RAS output CAN be used for memory interleaving to avoid delayed back to back accesses because of precharge. An additional fea- ture of the DP8422A is two access ports to simplify dual accessing. Arbitration among these ports and refresh is done on chip. By National Semiconductor Corporation