Quad Nor Unified Bus Receiver - National Semiconductor

The DS7836 DS8836 are quad 2-input receivers designed for use in bus organized data transmission systems inter- connected by terminated 120X impedance lines. The exter- nal termination is intended to be 180X resistor from the bus to the a5V Logic supply together with a 390X resistor from the bus to ground. The design employs a built-in input hys- teresis providing substantial noise immunity. Low input cur- rent allows up to 27 driver/receiver pairs to utilize a com- mon bus. Performance is optimized for systems with bus rise and fall times s 1.0 ms/V. By National Semiconductor Corporation